This invention relates to high frequency semiconductor devices and methods for their fabrication, and more particularly to gallium arsenide and other III-V semiconductor field effect transistors which have a vertical geometry.
The vertical field effect transistor described in U.S. Pat. No. 4,129,879, granted on Dec. 12, 1978 to W. Tantraporn and S.P. Yu, is a bulk conduction device employing three semiconductor regions of like conductivity type, preferably n-type gallium arsenide. Current flow is essentially normal to the surface as compared with horizontal devices in which current flow is parallel to the surface, and the vertical FET attains higher power at a higher frequency of operation than the conventional horizontal FET. The channel regions in an interdigitated device are in elongated fingers or mesa structures upstanding from the substrate which is the common source or drain, and gate metal surrounds the finger and forms an electronically blocking contact to the channel region, which extends completely across the finger from wall to wall without interruption. If constructed via the usual techniques, described in the above-mentioned patent, an epitaxial n-GaAs layer is deposited on an n.sup.+ substrate and undergoes masking, etching grooves between the fingers, and deposition of insulator and metal. It is difficult to realize a uniform semiconductor finger width or conducting channel width in the order of one to several microns as is required for a microwave frequency device, and this approach produces a channel region geometry that is wide at the substrate and narrower near the surface, restricting the space available for the drain or source contact at the top.